Patent Literature 1 discloses a semiconductor memory device. The semiconductor memory device comprises plural memory cells 20 disposed in a matrix form. More particularly, see FIG. 1 and FIG. 19 of Patent Literature 1.
FIG. 17 and FIG. 18 show reproductions of FIG. 1(a) and FIG. 19(a) of Patent Literature 1, respectively. As shown in FIG. 17, the memory cell 20 includes a substrate 11, a first gate electrode 12, a ferroelectric film 13, a semiconductor film 14, a source electrode 15s, a drain electrode 15d, a paraelectric film 16, a second gate electrode 17. As shown in FIG. 18, plural memory cells 20 are disposed in a matrix form.
Japanese Laid-pen Patent Application No. 2009-099606 corresponds to US Pre-Grant Patent Application Publication No. 2009/0097299.